utz wrote:Zilog wrote:Is it really more efficient than mine?
Not at all, yours is certainly more efficient! The idea was more to smoothen row transitions by speeding up the data loading. I think that worked out reasonably well, though as you can probably tell from the code it's not optimized at all yet.
8bit mixing with postscaling? Sounds intriguing, but to be honest I don't quite understand how that would work. Could you explain a bit more about this idea? In any case, I'd love to see a new engine from you, given the unique approach you took in Squeeker
Well, the key idea is, why do all the people use 8bit counters (DEC counter8; JR NZ 10T_padding; LD counter,divider; LD channel,spike) - this means the higher tone, the less accurate its frequency (divider has just few valid bits). this takes 26T/channel AFAIK.
But, there's different approach - phase accumulator instead of divider, there's no need for conditional jumps, you just add to 8bit "accumulator", ala
LD A,frequency; ADD A,L; LD L,A (no need to reload counters, carry is immediately available, you even can use ADD HL,DE to accomplish this, when the frequency of two channels is very different - bass carry-contributions from L to H could be neglected then etc.).
Carry then feeds (SBC A,A; AND scaling_val; ADD A,scaler8) another register, "scaler", where's accumulated scaling value, typically some power-of-two, repeatedly added and we can control octave this wat, ensuring that the frequency would be in perfect align with other octaves, because we add 128, 64, 32 or similar "nice" numbers. And, when the numbers are even a little bit biased, let's say by 7, 5 or so, then, PWM control degrades for very low widhts to "intermittent" pins, giving nice fades. You could even produce harmonics with "masking" of that scaler, in one channel.
You can think of it like a <#80-#FF>-range phase accumulator as "top-octave" generator, with secondary 8bit scaler fed by its pins, doing the "downscaling" stuff - volumes, timbre, intermittent PWM stuff.
I have this idea for more than 10 years, but still no time to implement it properly (some proof-of-concept has been made on PIC12F628 :-), where it takes 7 mcycles (7us for 4MHz xtal) per channel...
regards,
Zilogat0r